This invention relates to a phase startable clock device.
In a high speed digitizing instrument, an analog input signal is sampled and quantized during an acquisition interval under control of a sampling clock signal. The sampling clock signal may be, or may be derived from, a high frequency sinusoidal signal. It may be desired that the high frequency sinusoidal signal start with a known phase at a fixed time following a control signal transition that is representative of a trigger event. It is known to generate such a high frequency sinusoidal signal using a circuit known as a phase startable clock.
One form of phase startable clock comprises an oscillator and means for disabling and enabling the oscillator loop. The oscillator loop is in the enabled condition immediately before the control signal transition arrives. When the control signal transition arrives, the oscillator loop is temporarily disabled, so that the oscillator stops, and is then re-enabled. This synchronizes the oscillator output in time with respect to the control signal transition such that the oscillator starts with a known phase at a known time relative to the transition. Ideally, the oscillator should turn-off immediately and turn-on immediately upon receiving the control signal transition. In reality, however, the circuit elements within the oscillator require time to allow transients to settle. Therefore, the phase startable clock suffers a time penalty (the delay between receipt of the control signal transition and availability of the sinusoidal output signal). The time penalty depends on the Q of the elements within the oscillator.
Because of the desire to minimize the time penalty, prior phase startable clocks have used oscillators with low Q elements within the oscillator loop. However, an oscillator with low Q elements suffers long term jitter (instability of the oscillator's signal over the acquisition interval during which the analog input signal is sampled). Conversely, use of high Q elements to improve jitter performance results in an increase in the time penalty. The jitter performance for previous phase startable clocks has been limited according to a desire to minimize the time penalty.